Analog Layout Design Support Tool to Be Released

Seiko Instruments Inc. (Abbreviation: SII, COO: Akio Irie, Headquarters: 8,Nakase 1-chome, Mihama-ku, Chiba-shi, Chiba, Tel:+81-43-211-1111) will release an EDA tool (internal development code: Amper) developed in partnership by SII EDA Technologies Inc. (Abbreviation: SEDAT; President: Tadao Inoue), a semiconductor design tool and software development company located in Kitakyushu Science and Research Park and wholly owned by SII, and the University of Kitakyushu, Department of International Environment Engineering, Information and Media Sciences (Professor Yoji Kajitani and Associate Professor Shigetoshi Nagatake). The new EDA tool promises to be a great aid in analog layout design.

In recent years, the progress in information technology (portable and hand-held) devices in our information society has had an impact that has changed even societal conventions, and information technology devices are now indispensable in daily life. In this high-tech social environment, quick delivery (quick development) and high added value (features such as power saving and miniaturization) are in keen demand with regard to the release and manufacture of devices by information technology device companies. For this reason, the practice of integrating the analog circuitry of I/O (such as video and voice I/O) and wireless communication with the digital circuitry of control systems to create a low-cost, highly functional system chip has become mainstream.In order to meet the above demands, further progress in design automation is required. However, progress in the automation of analog circuit design lags behind that of digital circuit design, resulting in major problems at design locations.In order to prevent malfunction caused by factors such as the effects from the processing of arranged devices, the heat generated during operation or the differences in wiring dimensional standards, restrictions pertaining to symmetry and alignment are critical in analog circuit layout. The reason why automation has not progressed to date lies in the difficulties encountered when attempting to arrange the devices using an automated tool while taking into account these restrictions.

Amper uses circuit diagram layout information, netlists or existing layouts to identify layout restrictions, thereby facilitating the accommodation of restrictions in new layout designs. The function can be executed in a single step or used interactively with New-SX (see note below) Editor, supporting the designer in the various stages of layout design.Hereinafter, through the incorporation of routing tools, the development of a knowledge database pertaining to the layout and routing design process, and linkage with the routing tool and database, efforts will be made to build an environment which enables further support of the design process.

Note 1: New-SX
New-SX is the next-generation IC layout system newly developed by SII through the considerable experience and advanced technical capabilities gained during the development of the layout design tool SX-9000. The new layout system was developed to flexibly accommodate demands for characteristics such as IC enhanced integration, high speed, IC versatility and mixed-signal design. New-SX fully integrates an easy-to-use manual design environment with a powerful automatic design tool and a verification environment.

[Main Features]
1. Automatic identification of layout restrictions and layout topology
•Arranges an initial layout by utilizing circuit diagram layouts.
•Arranges layouts of identical form based on existing layouts.
•Identifies restrictions from netlists.

2. Editor linkage
•Simplifies the setting of restrictions using Windows compliant GUI.
•Equipped with a partial compaction function.

[Shipping and Sales Start Date]
April 2003

Contact Information
Press Contact
Seiko Instruments Inc.
Corporate Strategy
Corporate Communications Dept.
Fukuda, Yako

Product Inquiry
EDA International Sales Section

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